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Physical Design Engineer
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Physical Design Engineer
Xsight Labs- Posted 10 days ago
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Job Description
Description
Position Summary:
We are seeking an experienced and detail-oriented Physical Design Engineer to join our Advanced ASIC/SoC Development Team. In this role, you will be responsible for the complete RTL-to-GDSII physical implementation of high-performance, complex digital integrated circuits (ICs) built on advanced technology nodes (e.g., 7nm, 5nm, or below). You will collaborate closely with RTL design, architecture, DFT, and CAD team members to deliver power, performance, and area (PPA) optimized silicon on aggressive timelines.
Responsibilities
Position Summary:
We are seeking an experienced and detail-oriented Physical Design Engineer to join our Advanced ASIC/SoC Development Team. In this role, you will be responsible for the complete RTL-to-GDSII physical implementation of high-performance, complex digital integrated circuits (ICs) built on advanced technology nodes (e.g., 7nm, 5nm, or below). You will collaborate closely with RTL design, architecture, DFT, and CAD team members to deliver power, performance, and area (PPA) optimized silicon on aggressive timelines.
Responsibilities
- Design Implementation: Execute physical Design from RTL to GDS on advance technology of 5nm and below
- Timing and Power Integrity Closure: Perform Static Timing Analysis, Ensure Power Integrity and meet IR drop criteria.
- Physical Verification: Close DRC, LVS, ERC, ANT
- Work with global Engineer team to deliver design, ensuring design quality
- Education: BS, MS in Electrical Engineering, electronics Engineering.
- Minimum of 3 years of hands-on experience in physical design engineering for complex integrated circuits.
- Proficiency in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Genus)
- Scripting Languages: Strong skills in Tcl, Python, and Perl.
- Experience with advanced processes.
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About Company
Skills:
5nm and below), Advanced nodes (16nm, Static Timing Analysis (STA), Tcl Scripting, Tempus, DMMMC flow, STA methodologies, STA setup convergence reviews and signoff, Timing and leakage optimization, Multi-mode func scan atspeed, Logical physical aware ECO flows, Block-level and full-chip timing closure, Review unconstrained endpoints, Multi-voltage domain designs
Skills:
routing, IR drop analysis, Floor Planning, Antenna, LVS, powerplan synthesis, Cadence Innovus, automatic place and route tools, Physical Verification, ASIC physical implementation, Synopsys Fusion Compiler, physical verification procedures, Esd, timing closure techniques, Timing Closure, ERC, DRC, Clock Tree Synthesis, post-route optimization
Skills:
EDA tool chain - FusionCompiler, Shell, Static Timing Analysis, Python, Setup, Perl, Tcl, hold, Signoff Checks, IP integration, Timing Fixture, Synthesis, Physical Verification, Multiple power domain design flow, IREM flow, Extraction, Error Fixing, Clock Tree Synthesis, Requirement DRV checks, floorplanning, Make flow, Power Intent spec and checks, Script programming, Tk, Physical Design Implementation, Logic Synthesis, Place And Route
Skills:
Debugging, Routing, Shell Scripting, Automation, Static Timing Analysis, Python, Tcl, floorplanning, Congestion Mitigation, Power and Area Optimization, Synthesis, RTL-to-GDSII Implementation, Placement, Timing Closure, EDA Methodology Development, Physical Design Implementation, Clock Tree Synthesis