5nm and below), Advanced nodes (16nm, Static Timing Analysis (STA), Tcl Scripting, Tempus, DMMMC flow, STA methodologies, STA setup convergence reviews and signoff, Timing and leakage optimization, Multi-mode func scan atspeed, Logical physical aware ECO flows, Block-level and full-chip timing closure, Review unconstrained endpoints, Multi-voltage domain designs

routing, IR drop analysis, Floor Planning, Antenna, LVS, powerplan synthesis, Cadence Innovus, automatic place and route tools, Physical Verification, ASIC physical implementation, Synopsys Fusion Compiler, physical verification procedures, Esd, timing closure techniques, Timing Closure, ERC, DRC, Clock Tree Synthesis, post-route optimization

EDA tool chain - FusionCompiler, Shell, Static Timing Analysis, Python, Setup, Perl, Tcl, hold, Signoff Checks, IP integration, Timing Fixture, Synthesis, Physical Verification, Multiple power domain design flow, IREM flow, Extraction, Error Fixing, Clock Tree Synthesis, Requirement DRV checks, floorplanning, Make flow, Power Intent spec and checks, Script programming, Tk, Physical Design Implementation, Logic Synthesis, Place And Route

Debugging, Routing, Shell Scripting, Automation, Static Timing Analysis, Python, Tcl, floorplanning, Congestion Mitigation, Power and Area Optimization, Synthesis, RTL-to-GDSII Implementation, Placement, Timing Closure, EDA Methodology Development, Physical Design Implementation, Clock Tree Synthesis