Senior Physical Design Engineer
Senior Physical Design Engineer
leadsoc technologies pvt ltd- Posted 3 days ago
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Job Description
Senior Physical Design Engineer – EMIR
Location: Bengaluru
Experience: 5–10 Years
Role Overview
We are looking for a Senior Physical Design Engineer with strong hands-on expertise in EM/IR analysis and physical design sign-off for complex ASIC/SoC designs.
Key Responsibilities
- Perform EM/IR analysis, debugging and sign-off for block and full-chip designs.
- Analyze static/dynamic IR drop, electromigration and power integrity issues.
- Drive EM/IR closure through power-grid optimization, PG strengthening and physical ECOs.
- Work closely with Physical Design, STA, RTL, DFT and Power teams to resolve power integrity issues.
- Perform vector-based and vectorless EM/IR analysis and correlate results with design activity.
- Debug IR drop hotspots, EM violations and power-grid reliability issues.
- Support power planning, PG mesh/stripe optimization and power integrity sign-off.
- Analyze the impact of placement, routing, clocking and power distribution on EM/IR.
- Automate analysis and reporting using Tcl/Python/Perl.
- Support tape-out and sign-off closure for advanced-node designs.
Required Skills
- 5–10 years of ASIC/SoC Physical Design experience.
- Strong hands-on experience in EM/IR analysis and closure.
- Experience with Cadence Voltus, Ansys RedHawk or equivalent.
- Good understanding of power distribution networks, IR drop, electromigration and power integrity.
- Strong knowledge of physical design, P&R and sign-off flows.
- Understanding of STA, MMMC and advanced-node design challenges.
- Strong debugging and scripting skills.
- Experience with full-chip/block-level EM/IR sign-off preferred.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
physical design sign-off
static dynamic IR drop
physical ECOs
Cadence Voltus
power-grid optimization
PG strengthening
Ansys RedHawk
EM IR analysis
vectorless EM IR analysis
About Company
Skills:
PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, Ir, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure
Skills:
Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off
Skills:
C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation
Skills:
power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology