PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, Ir, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Tcl, Python, Perl, Physical Design flow, UPF, Fusion Compiler, Physical Verification, Innovus, Sta, ICC2, primetime, Tempus, low power design, CPF, MMMC concepts

redhawk , Verilog, Shell, PERL, Tcl, Fusion Compiler, Innovus, Calibre, VHDL, Starrcxt, place and route methodologies, low power physical design flows and methodologies, physical implementation and analysis tools, timing and signal integrity analysis, power integrity and reliability analysis, power grid planning and implementation, timing and metal-only ECOs, post-route timing optimization, placement and optimization, floorplan exploration and optimization, Clock Tree Synthesis