Design Verification, Senior Engineer (and above)
Design Verification, Senior Engineer (and above)
Quest GlobalFresher
- Posted 11 hours ago
- Be among the first 10 applicants
Job Description
- Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis
- Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification/Micro Architecture
- Testbench Development, Simulation/Debugging to identify and resolve any issues/failures of the design
- Work closely with Synthesis/PD teams to address any defects in Netlist, Timing SDF and ensure specifications are met
- Coverage analysis to detect uncovered areas that need further testing
- Documentation and reporting for progress tracking, detailed feedback to design teams, verification result
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Netlist
Simulation Debugging
Verification Item List
Verification Strategy
Testbench Development
About Company
Skills:
C, C++, Mac, Verilog, spice netlist, PHY, real number modelling, Ethernet Protocol, ethernet switch, systemverilog, formal verification, behavioural models, mixed-signal co-simulation, constrained random testing
Skills:
Simulation Debugging, Simulation Coverage Analysis, Netlist Timing SDF, Verification Strategy, Testbench Development, Test Plan Development, Documentation and Reporting
Skills:
prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, bug analysis, Gate level simulations, Regressions coverage analysis, ASIC SoC life cycle, Full chip test plan development modification, OVM UVM methodologies using SV, Test case development coding execution, Testbench development modification, Verification closure