C, C++, Mac, Verilog, spice netlist, PHY, real number modelling, Ethernet Protocol, ethernet switch, systemverilog, formal verification, behavioural models, mixed-signal co-simulation, constrained random testing

Simulation Debugging, Simulation Coverage Analysis, Netlist Timing SDF, Verification Strategy, Testbench Development, Test Plan Development, Documentation and Reporting

prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, bug analysis, Gate level simulations, Regressions coverage analysis, ASIC SoC life cycle, Full chip test plan development modification, OVM UVM methodologies using SV, Test case development coding execution, Testbench development modification, Verification closure