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Senior Static Timing Analysis (STA) / Physical Implementation Engineer
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Senior Static Timing Analysis (STA) / Physical Implementation Engineer
as powerup- Posted 21 hours ago
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Job Description
Pre-Layout Support & Constraint Development
- Support the development and maintenance of SDC constraints under the guidance of senior engineers.
- Assist with physical-aware synthesis using Design Compiler and Fusion Compiler.
- Help prepare netlists for scan stitching and develop timing constraints for test modes.
- Support UPF-based low-power intent modeling, including the implementation of isolation cells and level shifters.
- Generate preliminary pre-layout timing reports and review the results with senior team members.
- Perform post-layout static timing analysis (STA) using PrimeTime for assigned design blocks or operating modes.
- Identify setup and hold timing violations and assist with debugging and root-cause analysis.
- Support the implementation and validation of timing engineering change orders (ECOs).
- Assist in correlating timing results between pre-layout and post-layout stages.
- Develop knowledge of MCMM analysis, derating techniques, and timing analysis that accounts for physical effects.
- Collaborate with senior engineers to gain practical knowledge of Bos Semiconductors STA and physical implementation methodologies.
- Participate in timing review meetings and sign-off discussions.
- Adhere to established design flows, scripts, and quality assurance checklists.
- Continuously strengthen knowledge of STA fundamentals, Synopsys tools, and low-power design techniques.
More Info
Key Skills
timing engineering change orders (ECOs)
SDC constraints
MCMM analysis
Fusion Compiler
STA fundamentals
timing constraints for test modes
pre-layout timing reports
post-layout static timing analysis (STA)
scan stitching
UPF-based low-power intent modeling
derating techniques
low-power design techniques
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