Senior/Staff/Sr.Staff Engineer

Positions:

+ Synthesis/ STA/ Timing Sign-off

+ PnR

+ PV/ PISI and Physical Design Integration (Bump/RDL, IO & IP, PG, ESD)

Responsibilities & Opportunities:

+ Working directly with customer to clarify design specifications, implementation requirements, and sign-off criteria.

+ Handling from simple/small test chips to high demanding mass-production chips

+ Handling full chip Physical design implementation, including PKG/Bump/RDL design, IO/IP physical integration, PG planning and implementation, Synthesis/PnR/STA, Physical verification (DRC/LVS), ESD/EM/IRDROP and other reliability checks.

+ Cooperating with DFT/ Synthesis/ STA team to solve constraint-related issues and improve PPA.

Long term target:

We aim to build an implementation team where every engineer can expand his/her capabilities to take ownership of a full chip RTL to GDS.