DFT Engineer

JOB: DFT Engineer

LOCATION: HN/ HCMC

We are seeking an experienced Design for Test (DFT) Engineer with 10+ years of hands-on experience in ASIC/SoC DFT architecture, implementation, and validation. The candidate will be responsible for planning, developing, integrating, and verifying DFT features including Scan, MBIST, Compression, Boundary Scan, and ATPG to ensure high manufacturing test coverage and product quality.

Key Responsibilities

• Define and implement DFT architecture for complex ASIC/SoC designs.
• Develop and integrate Scan Chains, Scan Compression, MBIST, LBIST, and Boundary Scan (IEEE 1149.x) solutions.
• Drive DFT insertion and validation using industry-standard EDA tools.
• Develop ATPG patterns and analyze coverage reports for stuck-at, transition, path delay, and cell-aware fault models.
• Perform DFT signoff activities including scan chain verification, DRC checks, coverage closure, and pattern validation.
• Collaborate with RTL, Physical Design, STA, and Verification teams to ensure DFT requirements are met.
• Support silicon bring-up, debug, manufacturing test, and yield improvement activities.
• Analyze tester failures and provide root-cause analysis for production issues.
• Define DFT guidelines and best practices for future SoC programs.
• Mentor junior engineers and lead DFT activities across multiple projects.

Required Skills & Qualifications

Technical Skills

• Strong understanding of:
• Scan Architecture
• Scan Compression
• ATPG, MBIST/LBIST, JTAG/Boundary Scan
• Testability Analysis, Fault Modeling, Silicon Debug
• Hands-on experience with DFT tools such as:
• Synopsys DFT Compiler, Synopsys TetraMAX / TestMAX
• Cadence Modus, Siemens Tessent Scan, ATPG, MBIST
• Good understanding of: RTL Design (Verilog/SystemVerilog), SoC Architecture, Static Timing Analysis (STA), CDC/RDC Methodologies
• Physical Design Constraints
• Experience with scripting languages:Tcl
• Perl
• Python
• Shell Scripting

Domain Knowledge

• Experience in advanced technology nodes (16nm/7nm/5nm or below).
• Understanding of low-power DFT methodologies including UPF-aware DFT implementation.
• Knowledge of automotive, networking, AI/ML, mobile, or data-center SoC test requirements is preferred.

Education

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, VLSI, or a related field.

Desired Characteristics

• Strong analytical and debugging skills.
• Excellent communication and stakeholder management abilities.
• Ability to lead global cross-functional teams.
• Self-driven with a focus on quality and timely delivery.
• Experience mentoring engineers and driving technical decisions.

Preferred Qualifications

• Experience leading DFT execution for full-chip SoC programs.
• Knowledge of IEEE 1500, IEEE 1687 (IJTAG), and automotive standards such as ISO 26262.
• Experience working directly with ATE teams and production test environments.
• Proven track record of achieving high fault coverage and successful silicon bring-up.

Experience Required: 5-10+ years in ASIC/SoC Design for Test (DFT) engineering with end-to-end ownership of DFT implementation, ATPG, and silicon validation activities.

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, VLSI, or a related field.

Desired Characteristics

• Strong analytical and debugging skills.
• Excellent communication and stakeholder management abilities.
• Ability to lead global cross-functional teams.
• Self-driven with a focus on quality and timely delivery.
• Experience mentoring engineers and driving technical decisions.

Preferred Qualifications

• Experience leading DFT execution for full-chip SoC programs.
• Knowledge of IEEE 1500, IEEE 1687 (IJTAG), and automotive standards such as ISO 26262.
• Experience working directly with ATE teams and production test environments.
• Proven track record of achieving high fault coverage and successful silicon bring-up.

BENEFIT

• Hybrid working environment
• 18 paid leaves per year (including 12 annual leaves + 6 personal leaves).
• Insurance plan based on full salary + 13th salary + Performance Bonus.
• 100% full salary in probation period.
• Medical Benefit (Personal) and Family based on levels.
• Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
• Internal Training (Technical & Functional). Scope of English Training.
• Working from Mondays to Fridays.

*** Note: We highly appreciate your interest in this position of HCL Vietnam. After reviewing all applications, only qualified candidates will be contacted for the next steps within 15 days from date of submission. Thanks for your understanding.