Design Verification Manager, SSG
Design Verification Manager, SSG
Amazon Alliance10-12 Years
- Posted 9 days ago
- Be among the first 10 applicants
Job Description
Description
As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.
Role
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
Company - ADCI - BLR 14 SEZ
Job ID: A10481539
As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.
Role
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
- Architect and implement verification environments for complex functional blocks
- Create and enhance verification environments using SystemVerilog and UVM
- Develop comprehensive test plans through collaboration with design engineers, SW and architects
- Implement coverage measures for stimulus and corner-case scenarios
- Participate in test plan and coverage reviews
- Drive complex RTL and TB debugs
- Drive UPF based low power verification
- Contribute to verification activities across simulation and emulation platforms
- Work on creating the automation scripts to support DV methodologies
- Create infrastructure to performs system level performance analysis
- Manage a team of 6-8 DV Engineers
- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing
- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
- Knowledge of computer science fundamentals in object-oriented design
- 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks
- Managing a team of DV Engineers
- Experience with RTL development environments
- Proficiency in hardware description languages and verification methodologies
- Experience verifying complex IP blocks integrated into SOCs
- Experience with industry-standard tools and scripting languages (Python or Perl)
- Advanced degree in computer science, electrical engineering, or related field
- Experience in system-level debugging
- Knowledge of SoC architecture
- Experience in oral and written communication
- Experience with ARM and DSP instruction set architectures
- Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols
- Experience with formal verification methods Experience with Low power verification methods
- Experience with Baremetal processor environments
- Transaction level modelling expertise
- Familiarity with industry standard I/O interfaces
- FPGA and emulation platform knowledge
Company - ADCI - BLR 14 SEZ
Job ID: A10481539
More Info
Key Skills
low power verification
AMBA bus protocols
Baremetal processor environments
RTL development environments
test bench infrastructure
transaction level modelling
verification platforms
formal verification methods
emulation platforms
About Company
Skills:
Perl, Python, Test plan development, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, Transaction level modelling, systemverilog, DSP instruction set architectures, Industry standard I/O interfaces, Object-oriented design, AMBA bus protocols, RTL development environments, Baremetal processor environments, Verification methodologies, FPGA and emulation platform knowledge, Formal verification methods, UPF based low power verification, Hardware description languages
Skills:
Perl, Python, verification methodologies, low power verification, system level performance analysis, Uvm, systemverilog, RTL development environments, test bench infrastructure, emulation platforms, test plan development, automation scripts
Skills:
Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms
Skills:
C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling
Skills:
DDR, Pcie, SV, HBM, Design Verification, CXL, UCIe, Uvm