Perl, Python, Test plan development, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, Transaction level modelling, systemverilog, DSP instruction set architectures, Industry standard I/O interfaces, Object-oriented design, AMBA bus protocols, RTL development environments, Baremetal processor environments, Verification methodologies, FPGA and emulation platform knowledge, Formal verification methods, UPF based low power verification, Hardware description languages

Perl, Python, verification methodologies, low power verification, system level performance analysis, Uvm, systemverilog, RTL development environments, test bench infrastructure, emulation platforms, test plan development, automation scripts

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

DDR, Pcie, SV, HBM, Design Verification, CXL, UCIe, Uvm

Verilog, systemverilog, Rtl Design, Verification Manager, Test Bench