Sr Staff Engineer, Hardware Design
Sr Staff Engineer, Hardware Design
SiMa.ai- Posted 3 days ago
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Job Description
Description
Job Title: Sr Staff Engineer, Hardware Design
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)
Job ID: AI2553
Job Description
SiMa.ai is looking for an experienced hardware design engineer to own and evolve the RISC CPU IP used in our MLSoC™. You will work with architecture, verification, emulation, and physical design teams to define the microarchitecture, implement RTL, and make the modifications needed to meet performance, functionality, and SoC integration requirements.
You will contribute across the IP development lifecycle, from architecture and design reviews through synthesis, timing analysis, verification support, physical design collaboration, and silicon bring-up.
Responsibilities
Job Title: Sr Staff Engineer, Hardware Design
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)
Job ID: AI2553
Job Description
SiMa.ai is looking for an experienced hardware design engineer to own and evolve the RISC CPU IP used in our MLSoC™. You will work with architecture, verification, emulation, and physical design teams to define the microarchitecture, implement RTL, and make the modifications needed to meet performance, functionality, and SoC integration requirements.
You will contribute across the IP development lifecycle, from architecture and design reviews through synthesis, timing analysis, verification support, physical design collaboration, and silicon bring-up.
Responsibilities
- Own the RISC CPU core and drive its design, integration, and ongoing development.
- Work with the architecture team to define and refine the CPU microarchitecture.
- Modify and optimize the RISC CPU RTL to meet performance, functionality, and SoC integration requirements.
- Review RTL and design changes for quality, correctness, and maintainability.
- Perform or support synthesis, static timing analysis, equivalence checking, CDC analysis, and linting.
- Work with verification and emulation teams to resolve issues and support test and debug activities.
- Collaborate with physical design teams on floor planning, timing closure, and other implementation needs.
- Support IP integration, chip validation, bring-up, and characterisation.
- Coordinate with the ML accelerator and SoC teams to ensure the RISC CPU IP meets system-level requirements.
- Improve design methodology and flows for CPU IP development.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
- 8-11 years of professional experience in hardware IP design, SoC design, or a related area.
- Strong understanding of CPU architecture and experience developing or maintaining CPU IP.
- Experience with RTL design and SoC design methodology.
- Experience working across relevant parts of the design lifecycle, such as microarchitecture, synthesis, timing analysis, verification, emulation, physical design, or silicon bring-up.
- Experience with RISC CPU cores is plus.
- Experience with ARM CPUs and associated bus protocols.
- Experience integrating CPU IP into an SoC or working with accelerator-based systems.
- Takes ownership and follows through on commitments.
- Focuses on execution and results.
- Works effectively across teams and communicates clearly, including during difficult technical discussions.
- Demonstrates integrity, curiosity, and a collaborative approach.
More Info
Key Skills
RISC CPU IP
silicon bring-up
SoC design methodology
About Company
Skills:
static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking
Skills:
Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP
Skills:
Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB
Skills:
test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes
Skills:
Routers, DDR memory subsystem design and optimization, High Speed PCB design validation, Manufacturing support and product sustainment, Signal integrity SI and Power Integrity PI analysis and review, Timing synchronization and clock distribution systems, Power distribution network PDN architecture and design, 100G Ethernet systems, PCIe PAM4 based SerDes technology, High-speed Ethernet switches, Hardware debugging and root-cause analysis