Senior Process Engineer
Senior Process Engineer
STATS ChipPAC- Posted 18 days ago
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Job Description
Job Summary
We are seeking an expert Senior Process Engineer to focus on process development, characterization, and mass production scale-up for wafer assembly process steps such as back grinding, dicing, laser groove, edge trimming, lamination etc, in our advanced 2.5D/3D packaging research lab. In this technical role, your primary objective will be developing and delivering ultra-thin, high yield, high strength diced dies for 2.5D/3D advanced packaging.
Key Responsibilities
- Responsible for process development for Si/mold wafer backside grinding/thinning process, laser stealth dicing process, edge trimming process and lamination process for functional chips, with our R&D line.
- Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, and edge chipping for the Si wafers.
- Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.
- Characterize wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.
- New process development for DBG or SDBG process for super thin wafers processing with detailed process characterization.
- Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.
- Compile process SOP, WI, failure reports and engineering change documents; support ramp up process setup and process verification.
Key Requirements & Qualification
- Education: A Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline
- Experience: 3 to 6+ years of hands-on process engineering in wafer mounting, wafer dicing, wafer thinning or grinding, especially in handling advanced packaging wafers with more complex topology or stack
- Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production
- Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods
More Info
Job Type:
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Key Skills
lamination
wafer thinning
DOE matrix design
wafer assembly process
edge trimming
laser groove
back grinding
stealth dicing
process characterization
About Company
Skills:
quality assurance, thermo-mechanical treatment, Fmea, Spc, Sqc, Control Plan, MES implementation, Capa, SOP documentation, bonding wire coating processes, Process Control, mechanical deformation, micro-alloyed castings, Industry 4.0 transformation, automation initiatives
Skills:
Thin Film Characterization, Wafer Testing, plasma etch, Nuclear Reactor, Process Engineering, Process Logistics, design of experiments, plasma physics, Performance Profiling, Engineering Specifications, mass spectrometry, Synthetic Chemistry, Defect Prevention, Liaising with cross functional teams, Metrology and Inspection in Advanced Manufacturing, Doe
Skills:
Process setup characterization, DOE-driven optimization, Tungsten deposition, Process Documentation, Preventive Maintenance, Etch back processes, AMAT Centura tools, Continuous Improvement
Skills:
metallization , Fmea, APC, Spc, backfinish operations, semiconductor process control frameworks
Skills:
Equipment selection and qualification, Process Characterization, Cost Reduction, Statistical methods, Cycle time improvement, Process stability, Lithography Process, Productivity Improvement