Location: Ho Chi Minh City, Vietnam
Role Description
- The Design Verification Engineer will be responsible for developing and executing verification plans for digital designs, including creating testbenches, test cases, and coverage models.
- Daily tasks include performing functional verification of RTL blocks, supporting formal verification activities where applicable, analyzing results, identifying issues, and collaborating closely with design engineers to debug and resolve problems.
- The role also involves reviewing specifications and micro-architecture documents, ensuring alignment between design implementation and system requirements, and contributing to the continuous improvement of verification methodologies, automation flows, and best practices within the team.
Qualifications
- At least 4 years of experience in ASIC, SoC, IP, or digital design verification.
- Excellent analytical and problem-solving skills.
- Strong skills in RTL and testbench coding.
- Experience with SystemVerilog, SVA, UVM, and C/C++.
- Good English reading and writing skills; spoken English communication is a plus.
- Familiarity with one or more of the following:
- FPGA, ASIC, or SoC
- Object-oriented programming concepts
- Formal verification
- Low-speed IP or peripherals such as I2C, SPI, I2S, GPIO, WDT, or TIMER
- High-speed IP such as Ethernet, PCIe, USB, or ASA
- AMBA bus protocols such as APB, AHB, AXI-Stream, AXI, ACE, or CHI
