Verilog, C, Mac, formal verification, Ethernet Protocol, Mixed-signal co-simulation, systemverilog, PHY, Ethernet switch

Perl, Tcl, Verilog, Oop, Vcs, Digital Logic Design, Python, EDA Tools, systemverilog, Xcelium, AHB, low power design, Cadence Virtuoso, ADEXL, APB, Axi, Uvm, UPF, Cadence Genus, Spectre, Hspice, AMBA Bus, QuestaSim, Synopsys Design Compiler, spyglass