Senior Design Verification Engineer

Quick Overview

We are hiring on behalf of a client in the semiconductor / integrated circuit (IC) industry for a Senior IC Verification Engineer. This role is part of a verification team responsible for end-to-end pre-silicon verification activities, including system-level test planning through to tape-out and post-silicon support.

The position focuses on digital power IP verification using advanced methodologies such as SystemVerilog UVM, coverage-driven verification, assertions, formal verification, and UPF power-aware flows. The engineer will also collaborate closely with design teams and contribute to verification automation and quality assurance improvements.

Key Responsibilities

• Own and execute full verification lifecycle from system-level concept through tape-out and post-silicon support

• Develop pre-silicon test plans for digital power IPs

• Build and maintain testbenches using SystemVerilog UVM methodology

• Develop functional coverage models and assertion-based verification

• Perform formal verification including property checking

• Implement and learn power-aware UPF verification flows

• Collaborate with product designers to define functional and protocol requirements

• Review designs to identify potential failure points and define verification strategies

• Define verification environments, tools, and test strategies

• Develop automation solutions to improve verification efficiency

• Plan and execute structured test sequences and validation processes

• Conduct quality control inspections and verification sign-off activities

• Document final test procedures and support training of QC staff

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