System Verilog, Shell scripting, Python, Perl, Synopsys VCS, Uvm, Cadence Xcelium, Mentor Graphics QuestaSim

Mac, C, Verilog, formal verification, PHY, Ethernet Protocol, Ethernet switch, mixed-signal co-simulation, systemverilog

Perl, Python, EDA Tools, Mentor Graphics, Cadence, Synopsys, Uvm, systemverilog