Alternate Job Titles:
- Senior RTL Design Engineer
- ASIC RTL Senior Engineer
We Are:
At Synopsys, we drive innovations that shape how we live and connect. Our technology leads in chip design, verification, and IP integration, empowering high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You're a skilled engineer with a passion for RTL design and a drive for excellence. You thrive in collaborative environments, communicate effectively, and enjoy tackling complex challenges. Your technical expertise and enthusiasm for innovation help you deliver high-quality results.
What You'll Be Doing:
- Developing specifications and RTL for High Bandwidth Interface PHY IP.
- Collaborating with Verification teams to ensure design accuracy.
- Coordinating logic implementation phases across teams.
- Applying scripting skills for design automation.
- Participating in onboarding in Da Nang and transitioning to Hanoi or Ho Chi Minh City.
The Impact You Will Have:
- Advancing industry-leading high bandwidth interface IP.
- Ensuring robust design and verification processes.
- Driving innovation in RTL design and workflows.
- Enhancing productivity through automation.
What You'll Need:
- BS/MS/PhD in Electronics Engineering or Telecommunications.
- 2+ years in RTL design for ASIC or PHY IP.
- Experience with VCS, Verdi, Spyglass, Perl/TCL/Python.
- Knowledge of clock domain crossing, APB, JTAG.
- Good English communication skills.
Who You Are:
- Responsible, result-oriented, and self-motivated.
- Collaborative, adaptable, and eager to learn.
The Team You'll Be A Part Of:
You'll join a talented engineering team focused on delivering innovative PHY IP solutions, supported by experienced mentors in a culture of excellence.
Rewards and Benefits:
We offer comprehensive health, wellness, and financial benefits. Your recruiter will provide salary and benefit details during the hiring process.
