HCL Vietnam Company Limited belongs to HCLTech which is a global technology company, home to 222,270+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 30, 2022, totaled $12.1 billion.
Website: https://www.hcltech.com/
RESPONSIBILITIES:
- Logic Design IP/modules in SoC system
- Make specifications, architecture diagram
- Execute the RTL checker and clear all errors
- Perform Synthesis task and update constraints
REQUIREMENTS:
- 2- 4 YOE
- Good experience in RTL design skill set using Verilog, SystemVerilog
- Knowledge about AMBA protocol: AHB, APB, AXI is a must.
- Have experience in designing common IP (Memory, peripheral…)
- Basic knowledge of Synthesis and common EDA (DC, Fusion, Genus, Spyglass…)
- Knowledge about SoC system is a plus.
- Knowledge about Functional Safety, ISO26262 is a plus
- Knowledge about ECO is a plus.
- Provide transparent information, be agile in daily operations.
- Communicate fluently with teams and customers with a global mindset.
- Be innovative with excellent ideas in design and/or work-process optimization.
- Manage daily work, ensure that assigned tasks are completed on time and to the highest quality.
BENEFIT
- 18 paid leaves per year (including 12 annual leaves + 6 personal leaves).
- Insurance plan based on full salary + 13th salary + Performance Bonus.
- 100% full salary in probation period.
- Medical Benefit (Personal) and Family based on levels.
- Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
- Internal Training (Technical & Functional). Scope of English Training.
- Working from Mondays to Fridays.