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About Quest Global
For more than 25 years, Quest Global has strived to be the most trusted partner for the worlds hardest engineering problems. As a global organization headquartered in Singapore, we live and work in 18 countries, with 84 global delivery centers and offices, driven by 21,000+ extraordinary employees who make the impossible possible every day. Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.
About Quest Global Vietnam
Quest Global Vietnam is proud to be one of the pioneering semiconductor design service companies to establish a presence in Vietnam. We support leading chipmakers by providing a comprehensive range of turnkey silicon engineering, custom SoC, and ASIC services. We are a COMPLETE team that delivers Full Chip and Block Level RTL2GDS solutions to our clients.
Location: Ho Chi Minh, Da Nang, Ha Noi
Level: Lead and above
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Role Description
*Responsibility:
Responsible for the full physical design cycle from Synthesis to GDSII
Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis
Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures
Ensure the design meets performance, power, and area constraints
Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification
Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications
Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC)
Conduct parasitic extraction and analysis to optimize the performance of the IC
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Optimize designs for power, area, and performance
Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools
Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route
Work closely with team members to resolve design and flow
*Requirement:
Communicate with customers to make clear all requirements and guarantee the output of the team
Escalate issue with solution and follow up until the issue is closed
Proactively share and improve knowledge with other colleagues
6+ years of experience in Physical Design
Advance analysis/fixing skill (timing/congestion/signoff items), multitask handling
Ability to report directly to customers
Experience in leading a team and training a new member
Actively confirm/ask questions and no assuming
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Submit your CV to [Confidential Information]
Date Posted: 10/09/2025
Job ID: 125973377