Description
Invent the future with us
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.
As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
Join us at Ampere and work alongside a passionate and growing team - we'd love to have you apply!
About The Role
In this role, you will be responsible for ASIC implementation, including synthesis, floor-planning, place and route, timing closure, on our cutting edge ARMv9 based server on chip solutions. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry.
Ampere is looking for a motivated team player, who will be committed to helping us build a better server product.
What You'll Achieve
- Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off
- Run physical synthesis on large and medium size blocks
- Implement and verify other aspects netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc...
- Develop mid-end to back-end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc..
- Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners
- Perform timing closure across all corners to ensure successful tape-out following our aggressive deadlines
- Generate and implement functional ECO
- Run Logic Equivalent Check (LEC) from RTL to pre-layout/ post-layout netlist
About You
- Minimum 2+ years of development mid-end to back-end implementation flows
- Experience with Verilog or HDL languages and tools is a plus
- Experience in scripting languages (PERL, TCL, shell, etc.)
- Experience in ASIC methodologies and tools like Genus, Cadence Innovus, Synopsys Primetime, Cadence Tempus, LEC, CDC, etc.
- Physical design experience a plus
- Synthesis, place and route and Timing analysis experience
- Good English and Vietnamese communications skills, both speaking and writing
- BS/MS/Ph.D. in Electronic Engineering/Computer Engineering or equivalent
What We'll Offer
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits.
Benefits Highlights Include
- Premium healthcare, personal accident, and fully paid social insurance scheme as well as annual health check, so that you can feel secure in your health and financial future.
- Generous paid time off policy so that you can embrace a healthy work-life balance.
- Daily catered lunch, a variety of snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.
