Electronic Design Automation (EDA) tools, Layout versus schematic (LVS), Design rule checking (DRC), Ant, Sta, S-EM, Logic Synthesis, Pv, CTS routing, LVS, Dfm, Synthesis, DVD, Parasitic extraction and analysis, Placement, Floor-planning, Signal Integrity, Place And Route, P-EM, Timing optimization, Ir, EMIR, DRC, Low power check, Timing Analysis, Power and clock distribution

rc extraction , Synopsys physical implementation tool, IP block assembly, ARMv8, FinFET technology, Power and noise analysis, Asic Physical Design, Timing Closure, Power-planning, Chip-level routing, Power Clock Distribution, Floor-planning, Calibre DRC LVS physical verification tool, Place And Route

synopsys primetime , routing, automation, Scripting, Siemens Calibre, powerplan synthesis, Physical Verification, Cadence Innovus, LVS, ASIC physical implementation, post-route optimization, automatic place and route tools, ERC, Esd, EDA Tools, Timing Closure, DRC, Floor Planning, Antenna, Clock Tree Synthesis

power integrity , Tcl, Python, Perl, Static Timing Analysis, primetime, Cadence Innovus, Synopsys ICC2 Fusion Compiler, IR drop criteria, Genus, RTL-to-GDSII physical implementation

Tcl Scripting, Tempus, OCV effects, Timing Closure, DMMMC flow, noise crosstalk

EDA tool chain - FusionCompiler, Shell, Perl, Python, Tcl, Physical Design Implementation, Hold Setup Requirement, floorplanning, Signoff Checks, IP integration, Make flow, Timing Fixture, Synthesis, Physical Verification, Power Intent spec and checks, Extraction, script programming, DRV checks, Tk, Place And Route, Clock Tree Synthesis

Debugging, Routing, Shell Scripting, Automation, Static Timing Analysis, Python, Tcl, Power and Area Optimization, floorplanning, Congestion Mitigation, Synthesis, RTL-to-GDSII Implementation, EDA Methodology Development, Placement, Timing Closure, Physical Design Implementation, Clock Tree Synthesis