UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

python, Perl, System Verilog, DDR-IO verification, LPDDR JDEC specifications, Uvm, coverage driven verification methodology, LPDDR5

Spi, Uart, I2c, Ethernet, Can, DV firmware verification, GLS, Uvm, Specman, systemverilog, AMS CDC digital verification, post-silicon verification, AHB, C-based SoC design verification, UPF based verification, CSI, CPF, cybersecurity processes, AI ML based DV, formal verification, APB, Axi, functional safety, PAGLS

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Vcs, Pcie, Fpga, Arinc, Python, Tcl, Xcelium, Questasim, SV-UVM, Rivera-PRO, AXI4, DO-254, Asic verification

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles