Job Description: VLSI Design Trainer / Technical Instructor
About the Role
We are looking for an experienced VLSI Design Trainer to mentor and train the engineering interns on a complete RTL-to-GDSII design flow using industry-standard open-source and commercial EDA tools. The trainer will be responsible for designing the curriculum, conducting hands-on sessions, evaluating intern progress, and ensuring industry-readiness upon program completion.
Key Responsibilities
- Deliver structured training sessions covering the full RTL → GDS flow
- Conduct hands-on labs using licenced / open source tools (Yosys, OpenROAD, OpenSTA, Magic, and Sky130 PDK)
- Teach HDL coding in Verilog / SystemVerilog with UVM-based verification methodology
- Train interns on STA concepts using OpenSTA / Synopsys PrimeTime (if available)
- Guide interns through DRC / LVS sign-off using Magic and Netgen
- Introduce industry protocols: AXI4, SPI, I2C, UART
- Conduct scripting sessions in Python, TCL, Shell, and Perl
- Evaluate interns through assignments, mini-projects, and assessments
- Maintain daily session plans, attendance, and intern progress reports
- Coordinate with the internship coordinator for lab setup, tool installation, and scheduling
Required Skill Set
RTL Design & HDL
- Strong hands-on in Verilog / SystemVerilog RTL coding
- Knowledge of UVM (Universal Verification Methodology)
- Constrained-random verification and functional coverage
Synthesis
- Hands-on with Yosys (open-source) synthesis flow
- Familiarity with Synopsys Design Compiler (preferred)
- Understanding of timing constraints, SDC, and area/power optimization
Physical Design
- Hands-on with floorplan, placement, CTS, routing using any tool or open source (OpenROAD)
- Knowledge of OpenLane flow
- Familiarity with Cadence Innovus or Magic layout tool
Timing & Sign-off
- Static Timing Analysis using OpenSTA or Synopsys PrimeTime
- Setup/hold analysis, clock tree analysis, timing closure concepts
Physical Verification
- DRC / LVS using Magic + Netgen
- Awareness of Siemens Calibre (good to have)
PDK & Technology
- Hands-on with SkyWater 130nm (Sky130) PDK
- Understanding of standard cell libraries, LEF/DEF, SPICE models
Protocols & Interfaces
- Working knowledge of AXI4, SPI, I2C, UART interface protocols
- Ability to write and explain protocol-level testbenches
Scripting
- Python — automation, parsing, report generation
- TCL — EDA tool scripting (mandatory)
- Shell / Bash — flow automation
- Perl — log parsing (good to have)
Version Control
- Git / GitHub — branching, commits, pull requests, Markdown documentation
Qualifications
Criteria
Requirement
Education
B.E. / B.Tech / M.Tech in ECE, EEE, VLSI, or Microelectronics
Experience
2–6 years in VLSI physical design, RTL design, or verification
Industry background
Worked in semiconductor / EDA / chip design company preferred
Teaching experience
Prior training or mentoring experience is a strong plus
Tools familiarity
OpenROAD + Yosys (mandatory); Cadence/Synopsys (preferred)
Good to Have (Bonus Skills)
- Experience with Efabless / Google Open MPW shuttle tapeout
- Familiarity with FPGA flows (Vivado / Quartus)
- Knowledge of low-power design techniques (multi-Vt, clock gating, power gating)
- Exposure to formal verification tools (SymbiYosys, JasperGold)
- Prior experience handling batch sizes of 30+ students/interns
Industry
- Education Administration Programs
Employment Type
Part-time
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