System Design and Silicon Validation Intern (Connectivity)

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Systems Design & Validation team develops high-performance evaluation boards and reference designs for Marvell's next-generation datacenter PHY / retimer / DSP products operating at 200G+ per lane. We own the end-to-end platform cycle-from signal/power integrity analysis and component selection, through schematic and layout reviews, to board bring-up, measurement, and post-silicon validation.

As an intern, you'll work alongside experienced engineers across silicon design, system hardware, firmware, and validation to build real hardware platforms and use them to validate and optimize silicon performance.

This is more than a typical internship-it's a launchpad of your career as you are expected to not only learn and develop your technical competencies, but also integrate into Marvell's core behaviors and working culture that drives innovation and leading innovation in the industry. You'll gain hands-on experience, receive mentorship from industry leaders, and contribute to real projects that drive Marvell's product and R&D roadmap.

What You Can Expect

• Support the design and development of validation and evaluation boards used for silicon bring-up, characterization, and customer reference designs.

• Participate in the full hardware design cycle: circuit development, BOM selection, schematic capture, layout considerations, and platform evaluation.

• Learn and apply high-speed PCB design fundamentals, including SI/PI concepts and layout best practices for 200G+/lane systems.

• Collaborate with cross-functional teams (SI/PI, layout, analog/digital design, firmware) to build robust engineering platforms.

• Assist with board bring-up and bench testing using lab instruments (e.g., oscilloscopes, thermal controller, signal generators, .).

• Collect and analyze bench data to support post-silicon validation, characterization, and debug.

• Help characterize key electrical building blocks and system behaviors (e.g., TX, RX, CDR, CTLE, FEC, PCS, FLL, eAVS,)

• Support tuning/optimization efforts by correlating measurements to configuration parameters and operating conditions (PVT, robustness).

• Contribute to bench automation (Python) for repeatable measurements, data capture, and analysis.

• Write clear technical documentation such as test notes, lab reports, and application notes.

• Real project experience in one of the world's leading chip design environments

• Exposure to Marvell's core technologies, toolchains, and product workflows

• A mentorship path that could evolve into a full-time role or thesis opportunity

What We're Looking For

Minimum Qualifications

• Currently enrolled in a Bachelor's or Master's program in Electrical Engineering, Computer Engineering, or a related field.
• Solid fundamentals in electronics (circuit elements, analog basics, mixed-signal concepts).
• Exposure to or strong interest in high-speed design topics: signal integrity, channel behavior, PCB layout concepts.
• Basic understanding of silicon validation methodology and lab debug flow (or strong willingness to learn).
• Programming experience in Python (preferred) and/or MATLAB for data analysis and automation.
• Familiarity with schematic capture tools (coursework or project experience is fine).
• Self-motivated, team-oriented, and able to take ownership of tasks with guidance from senior engineers.
• Strong analytical/problem-solving skills and clear written/verbal communication.

Preferred Skills (Nice to Have)

• Familiarity with IEEE 802.3 standards and/or datacenter interconnect ecosystems (optical modules, AEC, MSAs).
• Prior project experience with SerDes systems, high-speed boards, or hardware bring-up.
• Hands-on experience with lab equipment (scope, signal generator, BERT, SSA etc.).
• Strong technical writing habits and disciplined documentation.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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