Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementation
Do Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Do Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
Develop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
Implement, enhance and maintain Synthesis, STA scripts and various automation flows
Work closely with logic design and PnR engineers on logic, timing, power and physical issues
