Senior/Staff ASIC Design Verification Engineer

2-4 Years

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Early Applicant

Job Description

Job Descriptions

Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.
Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.
Define, develop, and execute functional verification plans and test strategies.
Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
Generate VCD files and perform power analysis/reporting using PrimeTime PX.

Requirements:

Minimum of 2 years of experience in ASIC RTL design flow. (Candidates with extensive experience will be considered for senior/lead positions.)
Proficiency in RTL and GLS verification, with strong debugging capabilities.
Excellent teamwork and communication skills, with professional proficiency in English.
Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.