Senior SoC Architect

About the role

As a SoC Architect for AI-on-Edge Camera Gimbal products, you will own the architecture of a motion-control SoC that combines real-time brushless-motor control with on-device (edge) AI for camera stabilization and intelligent subject tracking. You will define the compute architecture — pairing an Arm CPU subsystem with an AI/NPU and DSP accelerator path — together with the high-resolution motor-control timers, fast current-sensing analog, camera and IMU interfaces. You will drive the device from concept through specification, IP selection, RTL hand-off and bring-up, and act as the technical authority on PPA and the real-time-plus-AI dataflow.

Responsibilities

As the SoC Architect (AI-on-Edge Camera Gimbal), you will:

- Define the top-level SoC architecture and microarchitecture for a gimbal/motion-control device, combining an Arm CPU subsystem with an edge-AI accelerator (NPU) and DSP data path.

- Architect the AI/ML inference subsystem for on-device vision (subject detection and tracking): NPU/DSP selection, on-chip memory and bandwidth budgeting, and the dataflow from camera to inference to motor command.

- Define the motor-control architecture for three brushless (BLDC/PMSM) axes — high-resolution PWM timers, synchronized multi-channel ADC current sensing, and the Field-Oriented Control (FOC) compute path.

- Specify the camera and sensor interfaces (parallel DCMI and/or MIPI CSI-2, IMU over SPI/I2C) and the on-chip interconnect (AMBA AXI/AHB/APB), address map, and clock/power-domain structure.

- Drive PPA and dataflow analysis balancing real-time motor-control determinism against AI inference throughput, latency and power within a handheld/embedded thermal and cost budget.

- Lead IP selection and make-vs-buy across CPU, NPU/AI, DSP (e.g. Cadence Tensilica, Synopsys ARC, CEVA), camera (MIPI), ADC and PLL IP, defining integration requirements.

- Author detailed architecture and microarchitecture specifications and partition the design into IP/sub-blocks for RTL and verification teams.

- Collaborate with AI/software and firmware teams on the model-deployment toolchain (quantization, operator support) and the FOC/stabilization firmware library.

- Support RTL, verification, DFT, physical implementation and silicon bring-up as the architectural reference.

Requirements

- Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.

- 10+ years of digital IC / SoC design experience, with 5+ years in an SoC architecture or lead microarchitecture role (exceptional candidates with fewer years considered).

- Proven experience defining SoC architecture that integrates an AI/NPU or DSP accelerator with a CPU subsystem, from specification through silicon.

- Strong knowledge of edge-AI / ML hardware: NPU/DSP architectures, fixed-point/quantized inference, on-chip memory and bandwidth optimization for neural networks.

- Deep knowledge of Arm CPU architecture and microarchitecture and expert understanding of AMBA (CHI, AXI, AHB, APB) interconnect, address mapping and clock/power domains.

- Knowledge of motor-control and mixed-signal: high-resolution PWM timers, ADC current sensing, and ideally Field-Oriented Control (FOC) of brushless motors.

- Familiarity with camera/imaging interfaces (MIPI CSI-2 / D-PHY, parallel DCMI) and IMU

- Strong grasp of memory subsystems and PPA trade-off analysis

- Proficiency in SystemVerilog and scripting (Python, PERL, shell) for modeling and flow automation.

- Good English and Vietnamese communication skills, both verbal and written.

Nice to have:

- Experience with camera gimbals, image-stabilization or robotics/motion-control products.

- Familiarity with AI frameworks and deployment toolchains (TensorFlow Lite, ONNX, TVM) and model quantization.

- Knowledge of DSP design, image-signal-processing (ISP) pipelines, and computer-vision algorithms.

- Embedded programming in C/C++; experience with architectural modeling and virtual prototyping.

- Solid fundamentals in the full IC design flow, DFT and ASIC concepts.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

- Competitive compensation package, aligned with capabilities and performance.

- 100% salary during the probation period.

- Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.

- Project bonuses when you join ODC (Offshore Development Center) projects

- Work with cutting-edge technologies including AI on Chip, 4K/8K Video Processing, and advanced semiconductor process nodes.

- Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.

- Access to professional training and development programs within FPT Corporation.

- Working hours: 9:00 AM – 6:00 PM, Monday to Friday.

Contact point

If you are interested in this position, please send your resume and cover letter to email: [Confidential Information] (Mobile phone: 0363904039)