POSITION: SENIORPHYSICAL DESIGN (BACK-END) ENGINEER
Location: Ho Chi Minh city/Da Nang city, Vietnam
Employment Type: Full – time
Report to: ASIC Design Senior Manager/Director
ABOUT CONNEXUS
Connexus is a fast-growing fabless semiconductor startup focused on AI chips and advanced chip design services. We aim to empower the next generation of AI workloads with cutting-edge technologies, while building a collaborative, innovative, and people-first culture. We are building a world-class engineering center in Vietnam to deliver advanced node silicon at global standards.
ROLE SUMMARY
CNX is looking for an experienced Physical Design Engineer to join our backend team working on advanced ASIC designs at FinFET technology nodes (7nm, 5nm, 2nm and below). You will own block-level and subsystem physical design from floorplan through GDS tape-out, working closely with front-end design and verification teams to deliver timing-clean, DRC-clean silicon on schedule.
KEY RESPONSIBILITIES
- Perform full-chip and/or block-level physical design implementation for advanced ASIC projects.
- Plan the chip floorplan - decide where blocks, macros, and I/Os go, and design the power grid to deliver stable power across the chip
- Run place-and-route (P&R) and clock tree synthesis (CTS) using Innovus or ICC2, and close timing across all PVT corners
- Analyze and debug issues related to PPA
- Develop and improve automation scripts and implementation flows.
- Sign off the physical design - clear DRC/LVS violations using Calibre, check IR drop and EM, and deliver a clean GDS ready for foundry submission
- Work closely with front-end and verification teams to resolve implementation issues, and contribute to PD flow scripts and automation
- Mentor junior engineers and contribute to technical knowledge sharing within the team.
REQUIREMENTS
- Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related fields.
- Minimum of 4 years of hands-on physical design experience in commercial ASIC projects
- At least 2 completed tapeout cycles at 16nm or below; FinFET node experience (7nm/5nm/2nm) strongly preferred.
- Demonstrable ownership of P&R and timing closure from floorplan through GDS sign-off
- Solid understanding of FinFET-specific design rules: metal pitch, via rules, fin snap, color-aware routing
- Proficient in Tcl scripting; Python scripting for automation is a plus
- Hands-on experience with Cadence Innovus or Synopsys ICC2 for P&R; PrimeTime or Tempus for STA; and Calibre for DRC/LVS sign-off
- Familiar with multi-mode multi-corner (MMMC) timing analysis and SDC constraint management
- Experience in methodology development and flow automation.
- Strong problem-solving mindset with ability to independently debug complex PD closure issues
- Clear communication in English for cross-functional collaboration with global clients and partners
- Strong team player, self-motivated, integrity, fast learner with a growth mindset.
WHY JOIN CONNEXUS:
- Competitive salary based on capability, full SHUI on salary
- Performance & project bonuses
- Private medical insurance.
- Mentorship from top industry experts
- Comprehensive CNX Academy training
Apply via email: [Confidential Information]
