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Description
- Would be involved in the digital design of internal platform or customer projects.
- Responsibilities include (but not limited to) Specification creation, micro-architecture development, RTL coding, and customer support etc.
- Responsible for block level design, simulations, optimization, etc.
- Work with Design Verification team and Physical Design team to take the product from RTL to GDSII.
- Prior experience on control loops, micro-controller integration, high speed peripherals, chiplet interconnect is an added advantage.
Report to: Technical Manager
Job Requirements
- Bachelor's/Master's degree in Electronics /Electrical Engineering.
- 4+ years of Industry experience.
- Experienced in RTL design using VHDL/ Verilog/ System Verilog.
- Strong Basics of Digital design.
- Exposure to micro-processor integration is an added advantage.
- Experience of working with high-speed peripheral design team is an advantage.
- Good communication skills and a positive working attitude.
- Inclination for automation is an added advantage (Exposure to Python).
Interview Process
3 rounds: 2 Technical rounds and 1 for Culture fit
Offices:
+ HCM: Dương Bá Trạc, Quận 8
+ Danang
Job ID: 149407991
Skills:
synopsys primetime , Usb, DDR, Pcie, Verilog, Ethernet, Cadence Xcelium, Mentor Graphics Questa CDC, systemverilog, Synopsys SpyGlass CDC, Synopsys VC SpyGlass, Synopsys VCS, Synopsys Formality, Axi, Cadence Conformal, AMBA, APB, Synopsys Design Compiler, AHB
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