Perform gate level netlist to GDS design independently including and not limit to floor planning, place & route, clock tree synthesis, timing sign off and physical verification.
Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge.
Work with manager to achieve assigned tape out target.
JOB REQUIREMENTS
Final-year students who are about to graduate or recent graduates in the following majors: Electronics & Telecommunications, Computer Engineering, Semiconductor Engineering or related fields.
Solid knowledge of CMOS, Physical design, IC design flow.
