- Job type: Full time
- Experience Level: Junior / Early Mid-Level Engineer (13 years)
- Location: Ho Chi Minh City, Vietnam
Responsibilities
- Support development of Foundation IP including Standard Cell Libraries, SRAM bitcells, and SRAM peripheral circuits for advanced semiconductor technologies.
- Participate in SRAM bitcell design, evaluation, and optimization for stability, performance, and power efficiency.
- Perform SPICE simulations to verify functionality, timing, power, and stability of SRAM bitcells, memory periphery circuits, and standard cells.
- Conduct SRAM bitcell analysis, including:
- Read / write margin
- Static Noise Margin (SNM)
- Leakage and retention behavior
- PVT variation impact
- Support characterization of timing, power, and leakage data across multiple PVT conditions.
- Assist in generating and validating Liberty (.lib) timing and power models for standard cell and memory IP.
- Analyze and debug circuit behavior and simulation results to ensure design correctness.
- Develop or maintain automation scripts for characterization flows, data processing, and validation.
- Collaborate closely with layout engineers, CAD teams, and design leads to ensure design quality and DRC/LVS compliant layouts.
- Participate in design reviews, validation checks, and documentation preparation for IP release.
Requirements
- Bachelor's or Master's degree in:
- Electronics Engineering
- Microelectronics
- Electrical Engineering
- Telecommunications
- Computer Engineering
- Physics, IT, Math & Computer Science; or related fields.
- 13 years of experience in semiconductor circuit design, memory IP design, or standard cell library development.
- Understanding of CMOS circuit design fundamentals and digital logic design.
- Basic knowledge of SRAM architecture and memory circuits.
- Familiarity with SPICE simulation tools (HSPICE, Spectre, or equivalent).
- Familiar with Linux/Unix environment.
- Ability to work effectively both independently and within a team environment.
- Strong analytical, debugging, and documentation skills.
- Proficient in written and spoken English.
Preferred Experiences
- Experience with SRAM bitcell design or memory IP development.
- Familiarity with standard cell library design and characterization flows.
- Knowledge of timing and power modeling (NLDM / CCS).
- Experience using EDA tools such as Synopsys or Cadence design environments.
- Experience with automation scripting (Python, Perl, or Shell).
- Research experience in VLSI circuit design, memory design, or open-source silicon flows is a plus.
Why join Connexus::
- Competitive salary based on capability, full SHUI on salary
- Private medical insurance.
- Mentorship from top industry experts
- Comprehensive CNX Academy training
Apply via email: [Confidential Information]
