Layout Design Engineer

About Connexus:

Connexus is a fast-growing fabless semiconductor startup focused on AI chips and advanced chip design services. We aim to empower the next generation of AI workloads with cutting-edge technologies, while building a collaborative, innovative, and people-first culture.

Working Location: Ho Chi Minh or Da Nang

Working Hours: 09h00 - 18h00

Junior/Fresh Layout Engineer Position

Responsibilities:

• Design and develop layout design for Embedded Memory IPs, Standard Cells, and IO Cells.
• Collaborate closely with Manager and engineering teams on assigned works.

Requirements:

• Bachelor's or Master's degree, Electronics Engineering, Electromechanics, Physics, Telecommunications; or related fields.
• Fresh graduates with GPA at least 2.5/4 or 7/10; or from 1 year experience in relevant jobs.
• Strong communication, documentation and analytical skills.

Senior Layout Engineer Position

Key Responsibilities:

- Design, develop, and modify layout designs for Embedded Memory IPs, Standard Cells, and IOs.

- Participate in building and enhancing layout flow for faster, higher quality design processes.

- Conduct layout verification and ensure compliance with design rules and specifications.

- Perform design reviews across global teams.

- Mentor junior layout engineers or interns.

- Stay updated with the latest industry trends and technologies to incorporate best practices in layout design.

- Managing a team of Embedded Memory Layout individual contributors and supervisors.

- Planning and establishing goals and objectives for the team, tracking employee goals and career development pathways.

- Coordinating activities for optimal results, including cost management, methods implementation, and staffing.

- Ensuring the team delivers high-quality layout designs that meet performance, power,

and size requirements.

Requirements:

- Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related fields.

- Good English communication skills is required

- Minimum of 5 years of experience in custom layout, memory design (SRAM, TCAM,...)

- Advanced knowledge of Custom Layout and a deep understanding of Embedded Memory Layout.

- Familiarity with layout entry tools (Cadence, Synopsys) and layout verification tools (Mentor Calibre, Synopsys ICV).

- Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.

- Proficiency in layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.

- Strong communication, documentation, and analytical skills.

- Strong team player, self-motivated, humble, honest, and willing to learn

Preferred Skills:

- Experience in using and optimizing EDA tools.

- Knowledge of advanced process technologies and layout verification methodologies.

Benefits:

- Competitive salary, performance bonuses, and retention schemes.

- Private health insurance for employees and dependents.

- Learning and growth opportunities, guided by top industry experts.

- Join a fast-paced startup environment with impactful projects shaping the semiconductor future