Experienced RTL Design Engineer (3+ Years of Experience)

Job Description

• Design and implement PAD/PFC logic for SoC products, including pin multiplexing, boundary scan, test functions, and I/O control logic using in-house PAD design tools and methodologies.
• Implement PAD logic based on design specifications, pinmux definitions, PAD-RTL/PAD-IO requirements, and integration guidelines.
• Generate, integrate, and validate PAD logic using in-house tools (e.g., PGA, SCAAPII), ensuring consistency between specifications and generated design outputs.
• Analyze and resolve design issues identified by RTL lint, CDC, synthesis, timing, and formal verification tools.
• Develop automation scripts using Python and Tcl to improve design productivity and flow efficiency.
• Review verification, formal verification, and signoff results to ensure design quality and completeness.
• Collaborate with verification, DFT, STA, backend, and architecture teams throughout the design lifecycle.
• Support PAD integration, signoff activities, and continuous improvement of PAD design methodologies and environments.

Job Requirement:

• Strong RTL design experience using Verilog/SystemVerilog.
• Understanding of digital design fundamentals, pin multiplexing, and I/O control logic.
• Good Python scripting skills; Tcl knowledge is a plus.
• Experience with SpyGlass Lint & CDC, synthesis (Genus/DC), and timing analysis tools (PrimeTime)
• Knowledge of formal verification (JG-CONN/JG-CSV/JG-FPV) is an advantage.
• Basic understanding of DFT, boundary scan, and backend implementation is a plus.
• Strong self-learning capability and ability to work with in-house design tools.
• Agile problem-solving, transparent communication, and strong collaboration skills.
• Ownership mindset with a focus on design quality and continuous improvement.