DFT Staff Engineer (7+ Years)

DFT Staff Engineer (7+ Years)

Work Location: Ho Chi Minh city

RESPONSIBILITIES

Implementation of DFT features into RTL/NETLIST using Verilog on Top/Block level.

Define DFT Architectures and Test planning.

JTAG, BSCAN, MBIST and Scan Compression implementation/verification.

ATPG and test coverage analysis using industry standard tools.

Making DFT-SDC for PNR & STA.

Pre-sim & Post-sim for DFT patterns.

Support silicon bring-up and debug.

Support Test Engineering on planning, patterns, and debug.

Collaborate with other cross functional teams on project execution.

Mentor and guide engineers, ensuring best practices and continuous improvement.

Own DFT design flow control, updates, QA, and deployment for project teams.

Enhance and maintain DFT flows using the latest EDA capabilities (Siemens Tessent).

JOB REQUIREMENTS

BS/MS in Electrical, Computer, or Computer Science.

7+ years of experience in DFT with a solid understanding of ASIC/SOC design flows.

Strong experience in DFT from design to silicon bringing up with latest Tessent features (Scan/Compression/ATPG with SSN, Memory BIST/Repair, DC/AC BSCAN). Experience with Mentor tools is a plus.

Analyze silicon test results, diagnose yield issues, and support production test teams.

Proficiency in English is an extra plus.

Automotive device DFT experience is an extra plus.

BENEFITS:

Competitive base salary.

13th month salary and project bonus.

Healthcare for employees and family.

Oversea travel.

International working environment with a professional, young & dynamic team.

HOW TO APPLY:

Please send your resume to HR at the email address of [Confidential Information] for screening.