Alternate Job Titles:
- DFT Engineer
- Senior Design-for-Test Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, leading in chip design, verification, and IP integration. Join us to help transform the future through continuous innovation.
You Are:
You are a skilled engineer with a background in electronics and proven DFT experience. You thrive in collaborative teams, enjoy problem-solving, and are eager to lead and mentor others. With a passion for quality and efficiency, you look for ways to improve processes and deliver robust solutions for chip design and integration.
What You'll Be Doing:
- Own DFT tasks at IP level: scan chain stitching, ATPG, simulation.
- Create timing constraints for mission and DFT modes.
- Work with design and physical implementation teams on synthesis and constraint validation.
- Support customer IP integration and silicon bring-up.
- Lead and coach DFT team members.
The Impact You Will Have:
- Improve testability and quality of IP cores.
- Speed up time-to-market for new chips.
- Support seamless SoC integrations for customers.
- Mentor team members and share best practices.
What You'll Need:
- BS/MS/PhD in Electronics or related field.
- 2+ years DFT design experience.
- Expertise in scan insertion, ATPG, JTAG.
- Experience with Synopsys tools (Design Compiler, VCS, TetraMAX) is a plus.
- Scripting skills (Perl, TCL, Python) are a plus.
Who You Are:
- Detail-oriented, analytical, and a strong communicator.
- Proactive, collaborative, and eager to mentor.
The Team You'll Be A Part Of:
Join our expert DFT Engineering team in Ho Chi Minh City, dedicated to advancing testability and reliability in semiconductor IP.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details about salary and benefits during the hiring process.
