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Design Verification Leader

  • Posted 11 hours ago
  • Be among the first 10 applicants

Job Description

Responsibilities:

  • Define SoC-level VPlan: block/top UVM environments, functional coverage model, code coverage targets, and formal property coverage. 
  • Lead and mentor 14 DV engineers; allocate block ownership, set quality gates, manage schedule to tape-out. 
  • Architect scalable, reusable UVM environments for constrained-random simulation, directed tests, and CI regression. 
  • Establish DV methodology: SVA assertion libraries, coverage-driven verification (CDV), and formal verification flows. 
  • Drive formal verification for critical control logic, bus protocol, and power-domain sequencing. 
  • Own simulation infrastructure: LSF/cloud regression, EDA tool config (VCS/Xcelium), results dashboards. 
  • Coordinate GLS, timing simulation, and power-aware verification with RTL and PD teams. 

Requirements:

  • Bachelor's or Master's in Electrical/Computer Engineering. 
  • 10+ years IC verification; 3+ years as DV lead or verification manager. 
  • Expert in SystemVerilog and UVM; strong SVA background. 
  • Proficient with Synopsys VCS, Cadence Xcelium, or Mentor QuestaSim. 
  • Hands-on with formal verification tools (JasperGold or VC Formal). 
  • Experience building coverage-closure plans and running regression farms at scale. 
  • Good English and Vietnamese communication skills. 

Nice to Have 

  • Hardware emulation platforms (Cadence Palladium, Synopsys ZeBu). 
  • Verification of AI accelerators, DSPs, or real-time processors. 

Benefits:

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

  • Competitive compensation package, aligned with capabilities and performance.
  • Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
  • Opportunities to expand your professional network with leading semiconductor partners.
  • Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
  • Access to professional training and development programs within FPT Corporation.
  • Working hours: 9:00 AM – 6:00 PM, Monday to Friday.

Contact Point:

If you are interested in this position, please send your resume and cover letter to email: [Confidential Information] (Ms. Thu Huong – Mobile phone: 036.390.4039).

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Job ID: 151851611

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