I. Senior/Leader Design Verification
Job Description
As a Senior Design Verification role, you will lead and run the full flow of verification including planning, managing, and delivering final result to customer.
Responsibilities
- Lead development and maintenance of verification environment at module and SOC level using UVM methodology.
- Use assertion-based verification and perform code coverage analysis to verify module or SOC level.
- Play as key technical expert role in analyzing spec and creating test cases for IP, subsystem and SoC level verification.
- Create plans, manage verification progress, report regular update to higher level, and provide technical leadership to junior members in review and deliverable.
- Join training and mentoring junior and fresher members to grow up team.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering.
- 5+ years experience in the area of digital IC verification. Experience in doing full steps of Design Verification Flow, especially there is experience in reviewing output with Client.
- Hand-on leading experience in planning, executing, and managing Design verification from design to tape-out is a plus.
- Experience in system Verilog and UVM verification methodology
- Experience in using EDA tools from Cadence (xrun, simvision, imc), Synopsys (vcs, verdi, urg)
- Knowledge and working experience in Image Processing SOC is a plus
- Knowledge and experience in Black-box verification is a plus.
II. Junior Design Verification Engineer
Job Description
As a Design Verification engineer, you will work as a member of the Verification team to create test plan and run the verification flow on Modules and SoC level.
Responsibilities
- Join development and maintenance of verification environment for module and SOC level using UVM methodology.
- Use assertion-based verification and perform code coverage analysis to verify module or SOC level.
- Participate in building up verification plan and creating test cases for module and SOC level verification.
- Perform code coverage analysis on module and SOC level.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering.
- 1+ years experience in the area of digital IC verification.
- Experience in system Verilog and UVM verification methodology
- Experience in using EDA tools from Cadence (xrun, simvision, imc), Synopsys (vcs, verdi, urg)
- Knowledge and working experience in one or more of the following is a plus:
- AMBA Protocol (AXI, AHB, APB).
- DMA, I2C, UART, and SPI.
- Knowledge and working experience in Image Processing SOC is a plus
- Knowledge and experience in Black-box verification is a plus.
Benefit & Perks
Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:
- Competitive compensation package, aligned with capabilities and performance.
- 100% salary during the probation period.
- Project bonuses when you join ODC (Offshore Development Center) projects
- Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
- Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
- Access to professional training and development programs within FPT Corporation.
- Working hours: 9:00 AM – 6:00 PM, Monday to Friday.
- Working in Ha Noi, Da Nang, Ho Chi Minh
Contact point
If you are interested in this position, please send your resume and cover letter to email: [Confidential Information] (Ms. Thu Huong – Mobile phone: 036.390.4039).
