Analogue Layout Engineer, CAD Engineer, IC Design Engineer

MITAS Technologies is inviting new Engineers to build new and great projects together, with real silicon products!

Check out details for each job here:

1-ANALOGUE LAYOUT ENGINEERS (JUNIOR AND SENIOR)

Position Overview:

We are looking for highly motivated Engineers to join our dynamic team. The ideal candidate will assist with the design, layout, verification, and optimization of analogue, mixed-signal, and power-management IC projects. The successful candidate will primarily use Tanner L-Edit but must also be proficient in using open-source layout tools (Magic, KLayout, SKY130/GF180 flows) and Cadence Virtuoso for customer-facing or IP handoff work. This position offers an excellent opportunity for professional growth and skill development in a collaborative environment. The role involves ownership of block-level and top-level analogue layout, verification, and support through tapeout.

Key Responsibilities

Layout Design: Collaborate with senior engineers to create high-quality analog layouts for ICs in accordance with design specifications, ensuring compliance with design rules and best practices.

Verification: Conduct layout versus schematic (LVS) checks, design rule checks (DRC), and parasitic extraction to ensure the integrity and performance of the designs.

Documentation: Maintain detailed documentation of layout methodologies, design processes, and necessary modifications for future reference.

Collaboration: Work closely with design engineers to understand design requirements and provide layout solutions that meet performance goals.

Tool Utilization: Work with open-source flows (Magic, KLayout, Tanner L-Edit and open PDKs) for layout design and verification.

Continuous Improvement: Participate in layout reviews and contribute ideas for improving the design process, methodologies, and tools.

Support mock tapeouts, prepare GDS and abstracts, and ensure correct compliance with foundry PDK requirements.

Qualifications

Education: Bachelor's degree in Electrical Engineering, Electronics, or related field.

Experience: 1-2 years of experience in analogue layout design within an IC design environment.

Technical Skills & Experience:

Strong understanding of layout-dependent effects, mismatch, symmetry, parasitics, and analogue performance optimization.

Working familiarity with open-source tools, particularly Magic, KLayout, and open-source PDKs

Able to write scripts (preferably Python, Tcl, or SKILL) to automate and improve processes.

Able to collaborate with circuit designers, understand critical paths, and produce first-time-right layouts.

Able to analyze problems and provide effective solutions on time.

Able to work independently and take ownership of deliverables.

Eager to learn and work in a team-oriented environment.

Strong communication and documentation skills.

2-SENIOR CAD ENGINEERS

Role Summary

We are seeking a Senior CAD Engineer to lead and maintain our semiconductor design infrastructure across analogue, RFIC, mixed-signal, and digital flows. The role covers Cadence tool support, ClioSoft-based design data management, open-source EDA workflows using GitHub, and scripting automation. You will ensure our design teams have a robust, efficient, and scalable environment from initial concept through to mock tapeouts and full signoff.

EDA Tools & Environment Support

- Maintain and support the full Cadence Virtuoso design environment, including library setup, techfiles, display files, simulation setups, and PDK integration.

- Manage and update LVS/DRC/PEX flows (Calibre preferred; PVS/Assura as required).

- Support designers with schematic, layout, simulation, netlisting, PEX, and mixed-signal flow issues.

- Troubleshoot PDK, model, and environment problems efficiently.

Design Data Management

- Administer ClioSoft SOS, including repository setup, project branching, access control, release tagging, and library baselining.

- Ensure data integrity, traceability, and clean handoff between design phases.

- Integrate GitHub into open-source tool flows (Xschem, Magic, KLayout) and maintain internal scripting repositories.

Scripting & Automation

- Develop and maintain automation scripts in SKILL, Python, Tcl, and shell for simulation automation, library consistency checks, batch regressions, flow setup, and environment configuration.

- Improve efficiency by building lightweight tools, wrappers, and templates for designers.

Open-Source EDA Flow Support

- Support open-source design flows (SkyWater/GF180 PDKs, Xschem, Magic, KLayout, OpenLane/OpenROAD).

- Manage GitHub repositories for scripts, PDK forks, and design collateral.

Tapeout & Mock Tapeout Support

- Lead mock tapeouts to ensure the team is familiar with signoff procedures.

- Own the tapeout checklist: DRC, LVS, PEX, formal verification, documentation, naming conventions, and data packaging.

- Coordinate with foundries on DRC decks, model releases, and submission requirements.

- Ensure reproducible builds and clean, audit-ready design drops.

Collaboration & Training

- Provide clear guidance to designers on best practices in tool usage, version control, and data management.

- Create onboarding documentation and maintain internal CAD wikis.

- Work closely with IT to manage compute servers, storage, FlexLM licensing, and backups.

Qualifications & Experience

- Strong experience in Cadence Virtuoso flow support and PDK management.

- Hands-on with ClioSoft SOS or equivalent semiconductor configuration management tools.

- Proven scripting ability in SKILL plus Python or Tcl.

- Experience with Calibre DRC/LVS/PEX signoff flows.

- Familiarity with open-source tools (Xschem, Magic, KLayout) and GitHub-based workflows.

- Previous participation in commercial tapeouts preferred; mock tapeout experience acceptable.

- Excellent problem-solving ability and strong communication skills.

3-IC DESIGN ENGINEERS (JUNIOR & SENIOR)

This role is ideal for recent Master's graduates or engineers with up to 3 years of industry experience who want to develop strong skills in analogue and mixed-signal IC design. You will receive mentoring from senior engineers while contributing to real silicon products.

Key Responsibilities

Assist in the design and simulation of analogue blocks such as op-amps, references, bias circuits, and LDOs.

Perform transistor-level analysis, corner simulations, and Monte-Carlo simulations under guidance.

Support layout engineers with matching requirements, floorplanning details, and layout reviews.

Help prepare documentation including block specifications, test plans, and simulation reports.

Participate in silicon bring-up and lab measurements using oscilloscopes, SMUs, power supplies, and other bench equipment.

Work with senior designers to support full-chip integration and tapeout activities.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field.

Good understanding of semiconductor devices and CMOS analogue fundamentals.

Basic knowledge of analogue building blocks (op-amps, current mirrors, bandgaps, LDOs, etc.).

Familiarity with commercial EDA tools such as Cadence Virtuoso/Spectre, Synopsys Custom Designer, or Mentor/Siemens tools (university-level exposure acceptable).

Basic lab skills and willingness to learn silicon bring-up and debugging.

Strong analytical skills and willingness to work through detailed simulations and documentation.

Preferred / Bonus Skills

Coursework or project experience in analogue design, power management ICs, or mixed-signal design.

Programming skills (Python, MATLAB/Octave, or C) for simulation automation or data analysis.

Experience with PCB design tools or basic embedded systems is a plus.

Internship experience in IC design or hardware development.

Personal Attributes

Eager to learn and grow into a fully independent IC designer.

Self-motivated, responsible, and able to work systematically.

Strong problem-solving mindset and attention to detail.

Good communication skills and willingness to work in an international engineering environment.

Location

Hanoi, Vietnam

Training opportunities and mentoring provided.

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