EDA tool chain - FusionCompiler, Shell, Perl, Python, Tcl, floorplanning, Signoff Checks, Timing Fixture Hold Setup Requirement, IP integration, Make flow, Synthesis, Physical Verification, Power Intent spec and checks, Extraction, script programming, DRV checks, Tk, Physical Design Implementation, Place And Route, Clock Tree Synthesis

synopsys primetime , routing, automation, Scripting, Siemens Calibre, powerplan synthesis, Physical Verification, Cadence Innovus, LVS, ASIC physical implementation, post-route optimization, automatic place and route tools, ERC, Esd, EDA Tools, Timing Closure, DRC, Floor Planning, Antenna, Clock Tree Synthesis

Tcl Scripting, Tempus, OCV effects, Timing Closure, DMMMC flow, noise crosstalk

Debugging, Routing, Shell Scripting, Automation, Static Timing Analysis, Python, Tcl, Power and Area Optimization, floorplanning, Congestion Mitigation, Synthesis, RTL-to-GDSII Implementation, EDA Methodology Development, Placement, Timing Closure, Physical Design Implementation, Clock Tree Synthesis