Perl, Python, Tcl, primetime, Genus, Cadence Innovus, Fusion Compiler, Synopsys ICC2

5nm and below), Advanced nodes (16nm, Static Timing Analysis (STA), Tcl Scripting, Tempus, DMMMC flow, STA methodologies, STA setup convergence reviews and signoff, Timing and leakage optimization, Multi-mode func scan atspeed, Logical physical aware ECO flows, Block-level and full-chip timing closure, Review unconstrained endpoints, Multi-voltage domain designs

cadence spectre , ltspice , Electronic Circuits, C, Linux Shell Scripting, Python, Tcl, Synopsys Custom Compiler, SRAM memory cell operations, MOSFET characterization, semiconductor device physics, Digital IC design, Hspice, CMOS circuit theory, Cadence Virtuoso

can bus , MATLAB, Python, Data Analysis, control theory, feedback control, Vehicle Dynamics, trajectory tracking, MPC, Simulation, nonlinear control, LQR

Verilog, Python, Tcl, LINT, primetime, systemverilog, CDC synthesis, spyglass, Genus DC, JG-CONN, formal verification, JG-CSV, timing analysis tools, JG-FPV

EDA tool chain - FusionCompiler, Shell, Static Timing Analysis, Python, Setup, Perl, Tcl, hold, Signoff Checks, IP integration, Timing Fixture, Synthesis, Physical Verification, Multiple power domain design flow, IREM flow, Extraction, Error Fixing, Clock Tree Synthesis, Requirement DRV checks, floorplanning, Make flow, Power Intent spec and checks, Script programming, Tk, Physical Design Implementation, Logic Synthesis, Place And Route