AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Fpga, Asa, Pcie, Technical Leadership, System Verilog, Uvm, Maxim GMSL protocol standard, USB 3, VIP development, FuSa verification, Effort and schedule estimation tracking, MIPI, AMS Verification, Grounds up verification environment development, TI FPD

Perl, Python, Tcl, DDR5 LPDDR5 verification, SVA, functional coverage, VIP emulation, DDR PHY verification, SystemVerilog UVM, FPGA prototyping, debug and root-cause analysis

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Coverage, Assertion checkers, Uvm, VMM Test Harness, MIPI, Validation plan, System Verilog HVL, Scenario creation

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design