C, C++, Mac, Verilog, spice netlist, PHY, real number modelling, Ethernet Protocol, ethernet switch, systemverilog, formal verification, behavioural models, mixed-signal co-simulation, constrained random testing

Perl, Tcl, Verilog, Oop, Vcs, Digital Logic Design, Python, EDA Tools, systemverilog, Xcelium, AHB, low power design, Cadence Virtuoso, ADEXL, APB, Axi, Uvm, UPF, Cadence Genus, Spectre, Hspice, AMBA Bus, QuestaSim, Synopsys Design Compiler, spyglass