Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

DDR, Pcie, Ethernet, GIC, CMN, Low-Speed Peripherals, SMMU, RISC-V Cores, eMMC, CoreSight, SoC-level Design Verification, SV, Low-Power Verification, ARM v8 v7 Cores, Uvm, UPF

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation

Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog

Java, Pcie, Perl, Verilog, Python, System Verilog, coverage-based verification methodology, assertions, Intel Quartus, Uvm, Xilinx Vivado

Testplan, Perl, Verilog, Shell scripting, Python, System Verilog, testbench, Pre-silicon verification, Coverage Assertion writing, Uvm

Design-for-Debug (DFD) and Verification Debug, Verilog, Usb, Pcie, UVM-based Verification Environment Development, Verification Planning Execution, SoC Subsystem Verification, Testbench Development, Interconnect Verification, systemverilog, Functional Coverage, UFS, Axi, Assertions SVA, EMAC Ethernet, Coverage-driven Verification, AHB, AMBA ATB Protocols

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure