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Senior Staff Engineer – Design Verification
Location: Bengaluru, India
Experience: 10–15 Years
About the Role
We're looking for a Senior Staff Design Verification Engineer to lead verification of next-generation CPU and SoC platforms. You'll define verification strategies, architect scalable UVM environments, and drive verification closure for complex CPU and high-performance SoC/IP designs.
What You'll Do
What We're Looking For
Join us to architect and verify next-generation CPUs and SoCs powering tomorrow's high-performance computing and AI platforms.
Job ID: 152332027
Skills:
Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, C Language
Skills:
Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog
Skills:
Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion
Skills:
IP SoC verification, ASIC-SoC design verification, systemverilog