Lead Design Verification Engineer
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Design Verification - Prior experience in PCIe,Ethernet,CXL,USB And DDR
Experience: 7 to 12 Years
Notice: 30days to immediate joiner
Location: Bangalore
Qualifications: Bachelor's or Master's degree in Electrical Engineering
Job Summary:
Prior experience in PCIe,Ethernet,CXL And DDR
Good in SV UVM
Strong in SV, UVM, PCIe,Ethernet,CXL,USB
PCIe,Ethernet,CXL,USB networking protocol verification
Preferred Skills:
Experience in leading teams and managing projects.
Knowledge of additional verification methodologies and tools.
Strong communication and interpersonal skills.
Ability to work in a fast paced environment and manage multiple priorities
Kindly share me your resume at [Confidential Information]/ [HIDDEN TEXT]
Job ID: 152722273
Skills:
Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA
Skills:
Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs
Skills:
System Verilog, Axi, dv methodologies and tools, ACE-Lite, Bus protocols like AHB, Ace, Digital design concepts, LPDDR5 protocols, Debug, Uvm
Skills:
Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory
Skills:
Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design
