rtl verification , Automation, Verilog, Python, FineSim, AMS verification, Transistor-level verification, Mixed-signal coverage analysis, AI-assisted solutions, Circuit Analysis, Uvm, Functional code assertion, systemverilog, CMOS design fundamentals, Hspice, Mixed-signal architectures, Semiconductor device behavior, Spice, EDA workflow optimization

temperature sensors , bandgap references , DNL, ADEXL, op-amps, INL, biasing circuits, Layout XL, THD, precision analog circuits, CMOS technologies, DC operating point, noise, Stability, LDOs, mixed-signal circuit design, AMs, Cadence Virtuoso suite, Spectre, Sigma-Delta converters, Schematic Maestro, AC simulations, frequency response, ip development, mismatch analysis

System Integration, Matlab, Signal Grounding, Monte Carlo Analysis, Physical Layout Management, Top-level Verification, Block-level Modeling, AMs, Post-layout Parasitic Extraction, Architectural Tradeoff Analysis, Block-level Topology Selection, IC System Partitioning, Spectre, Worst-case Identification, Schematic Generation, Simplis, Routing Tradeoffs, Device Physics Knowledge

circuit testing , clocking circuits, analog to digital converters, CMOS technologies, Circuit Simulation, LDO, analog power circuits, analog fundamentals, Analog Electronics, analog behavior modeling

UNIX, Layout tradeoffs, Layout verification tools, Analog Power IC design, Production test applications, AC DC analysis, CMOS BiCMOS fabrication processes, MOS transistors, Signals systems and transforms, Mixed Signal Design, Analog Circuit Design, Feedback systems, Modeling Tools, Poles zeros compensation, End to end design flow, Circuit simulation tools, device physics, Loop dynamics

Analog Circuit Design, Design Verification, Monte Carlo analysis, Modern CAD tools, Silicon validation and debug, Analog layouts, Simulation and Verification, Transistor level design flow, Schematic generation