DC-DC converter, Process technologies, Large signal analysis, Analog IC design, Simulation Tools, Biasing, Device behaviour, Power IC solutions

synchronicity , Unix, Perforce, Python, Shell Scripting, Git, Perl, Tcl, substrate noise analysis, Skill, Cadence custom IC Virtuoso platform, Cadence SKILL, starRC, Layout Automation, Calibre Physical Verification, ICV LVS, Analog Design environment, EMIR drop, agentic AI flows, finesim, Parasitic Extraction, PrimeSim, Virtuoso suite, SVRF

static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

Integration, Programming Languages, architecture and design tools, scripting tools, ASIC Design, design verification methods, RTL to GDS Flow, Verification, virtuoso, Validation

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design