Perl, Vcs, Python, Tcl, Verdi, Xcelium, ARM CPU Subsystem CPUSS verification, Uvm, systemverilog, AMBA CHI coherency and interconnect protocols

SV, PSS, Uvm

Pcie, Perl, Python, Verdi, Cadence Xcelium Simulator, CHI, Ace, GPUs, JasperGold, ARM CPU, AMBA protocols, Uvm, Synopsys VCS, ATB, Axi, HBM, Network on chip, LPDDR, DLA, VC Formal

C, Verilog, Ovm, Perl scripting, Python, System Verilog, VMM, Axi, Uvm, AHB

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage

Perl, Python, Tcl, RISC-V architecture, systemverilog

Verilog, formal verification, power-aware verification, Uvm, gate-level simulation, systemverilog, ASIC verification methodologies

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up