Perl, Python, Tcl, UPF, power simulation on VCS, UVM Test Bench development

Excel, Python, Ms Word

Liberty .lib, Python, Tcl, pulse-width verification, OCV, setup hold analysis, ETM timing model generation, ONFI PHY, Cadence Tempus, DDR PHY, Innovus, MMMC timing analysis, Cadence digital implementation and signoff flow, IO Expander, POCV methodologies, Genus, AI ML-enabled EDA methodologies, recovery removal checks, SDF generation, AOCV

synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff

Perl, Python, Tcl, FineSim, CTS, POCV concepts, Hspice, primetime, Monte Carlo analysis, STA tools, STA fundamentals, cross-talk, ICC2, Spice simulations, Tempus, Innovus, Signal Integrity, scripting proficiency, Timing Constraints, Parasitic Extraction, noise, ASIC back-end flows, AOCV

Computer Engineering, Tcl, low-power designs, Computer Science, Electrical Engineering, coding constraints

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre